This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree.
- 5 stars58.53%
- 4 stars28.25%
- 3 stars7.11%
- 2 stars3.04%
- 1 star3.04%
来自HARDWARE DESCRIPTION LANGUAGES FOR FPGA DESIGN的热门评论
I think this is a good start in learning how to write VHDL and Verilog.
I would like to see a next level course or recommendations for further writing code.
I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .
The course helped in showing the different styles of the Verilog and VHDL coding.
Understood the advantages of Verilog and VHDL in real life applications
The Verilog course was very good.
However the vhdl course could have been better.Needed a bit more clarity on the assignments.The lectures could have used a bit more explanation.