Very well explained the concepts.

Good Study material for Beginner

very informative and practical

Really a great experience!!

very impressive materials

this course is very nice.

Very good for beginners

High Value Course !

Very good course

Awesome course

it's awsom

Excellent

very good

good one

thanks

Nice.

nice

good

This class gave me a good basic understanding of HDL.  As I proceeded into later classes, I appreciated that this was an intro.  I had to read and learn a bit more to get the rest of the classes in the specialization done.  The FIFO assignment was frustrating as it seems ill-specified.  I couldn’t get the VHDL version right despite several attempts.  The auto grader for assignments can be nonsensical and provide very limited feedback as to what you did wrong and how you can improve your grade (or learn from your mistakes).  To make matters worse, there’s no written rubric as to how points are awarded.  All that said, I felt the class did a good job of helping me get a good ground in hardware description languages. I wish there would have been an assignment to develop a test bench. I also would have liked to hear about UVM.

feeling satisfactory after successfully completing the course. the instructors were the expert of the topic and explained very well. some of the programming assignments require more clarifications and learning which i found missing in the videos. videos are not enough to complete those assignments.

i am very happy to have this certification and would love to be the part of more learning by the coursera.

The course gives a good overview for the HDL. However, the assignments templates needs to be revised because there were some errors. Also, the requirements sometimes are vague, there is no specific specifications like synchronous/asynchronous signals active high/low clock. But, overall it was good time to revise HDL. I am looking forward to be involved in more advanced courses related to the FPGAs.

The course content was worthier and good. But the assignments and the methodology of assessing the assignments were not rigorous. The questions were not clear and elaborate. Once I uploaded a wrong Verilog code but I got 10/10 for that assignment. I don't know how. The course content was really good. But the method of evaluating the assignment could be made better.

A good combination of introduction to VHDL and Verilog. Cover essential topics for design and test implementation. There are rooms to improvement regarding the assignments description. Also, having the test benches encrypted is fine, but better to make it open source for students once they have get enough grades for that specific problem.

It is a nice course, I have learned a lot!. However, it can be better if the programming assignments had more comments or hints to debug your codes and complete with the test bench that grade every code. I know Verilog before take this course, but I learned new useful technical and theoretical knowledge.