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学生对 科罗拉多大学波德分校 提供的 Hardware Description Languages for FPGA Design 的评价和反馈

498 个评分


This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own....



Jun 6, 2021

I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .


Feb 20, 2022

There are so much use cases that i can apply in my life. thanks so much for giving the psychology know how into the lecture to help us in understanding the root course


76 - Hardware Description Languages for FPGA Design 的 100 个评论(共 144 个)

创建者 P S

Aug 6, 2020

Very well explained the concepts.

创建者 Ashish S

Oct 1, 2020

Good Study material for Beginner

创建者 Kondapally M R

Jun 24, 2020

very informative and practical

创建者 Abdul A

Nov 27, 2020

Really a great experience!!

创建者 wei z

Oct 18, 2021

very impressive materials


Aug 31, 2020

this course is very nice.

创建者 Vinayakumar B

May 26, 2020

Very good for beginners

创建者 Ovidiu S

Nov 17, 2020

High Value Course !

创建者 Rinson V

Aug 17, 2020

Very good course

创建者 Mucha. S r

Aug 27, 2020

Awesome course

创建者 Yassine F

Oct 24, 2022

it's awsom

创建者 Dr. J V S

Nov 13, 2020


创建者 segu v n k

Oct 29, 2020

very good

创建者 Adil A

Apr 13, 2022

good one

创建者 Mohsen s

Jan 17, 2023


创建者 Michael M

Jan 27, 2023


创建者 Alikhan K

Nov 11, 2022


创建者 Penaganti G

Jan 10, 2022


创建者 Sanjana A R

Jul 11, 2021

创建者 Greg H

Dec 18, 2022

This class gave me a good basic understanding of HDL.  As I proceeded into later classes, I appreciated that this was an intro.  I had to read and learn a bit more to get the rest of the classes in the specialization done.  The FIFO assignment was frustrating as it seems ill-specified.  I couldn’t get the VHDL version right despite several attempts.  The auto grader for assignments can be nonsensical and provide very limited feedback as to what you did wrong and how you can improve your grade (or learn from your mistakes).  To make matters worse, there’s no written rubric as to how points are awarded.  All that said, I felt the class did a good job of helping me get a good ground in hardware description languages. I wish there would have been an assignment to develop a test bench. I also would have liked to hear about UVM.

创建者 Lalit B

Mar 4, 2020

feeling satisfactory after successfully completing the course. the instructors were the expert of the topic and explained very well. some of the programming assignments require more clarifications and learning which i found missing in the videos. videos are not enough to complete those assignments.

i am very happy to have this certification and would love to be the part of more learning by the coursera.

创建者 Samer A A

Jul 7, 2020

The course gives a good overview for the HDL. However, the assignments templates needs to be revised because there were some errors. Also, the requirements sometimes are vague, there is no specific specifications like synchronous/asynchronous signals active high/low clock. But, overall it was good time to revise HDL. I am looking forward to be involved in more advanced courses related to the FPGAs.

创建者 Sangeerth P

Jun 29, 2020

The course content was worthier and good. But the assignments and the methodology of assessing the assignments were not rigorous. The questions were not clear and elaborate. Once I uploaded a wrong Verilog code but I got 10/10 for that assignment. I don't know how. The course content was really good. But the method of evaluating the assignment could be made better.

创建者 pedram k

Apr 21, 2020

A good combination of introduction to VHDL and Verilog. Cover essential topics for design and test implementation. There are rooms to improvement regarding the assignments description. Also, having the test benches encrypted is fine, but better to make it open source for students once they have get enough grades for that specific problem.

创建者 Jhoan E L E

Oct 9, 2021

It is a nice course, I have learned a lot!. However, it can be better if the programming assignments had more comments or hints to debug your codes and complete with the test bench that grade every code. I know Verilog before take this course, but I learned new useful technical and theoretical knowledge.