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学生对 科罗拉多大学波德分校 提供的 Hardware Description Languages for FPGA Design 的评价和反馈

497 个评分


This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own....



Jun 6, 2021

I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .


Feb 20, 2022

There are so much use cases that i can apply in my life. thanks so much for giving the psychology know how into the lecture to help us in understanding the root course


126 - Hardware Description Languages for FPGA Design 的 143 个评论(共 143 个)

创建者 J S

Aug 5, 2020


创建者 Artur K

Oct 9, 2022

The course is split into 2 weeks of VHDL and 2 weeks of Verilog, with two different instructors. Unfortunately, the first 2 weeks are really dragging down the quality of the course. They are riddled with bad explanations, omissions, and plain errors throughout. I'd go as far as to say the student learns the contents of those weeks because of the reading materials (which do a good job explaining what's actually going on), and despite the instructor video lectures , which are just leading the student astray.

The programming assignments in both parts of the course leave a lot to be desired with regard to the quality of specifications. They frequently don't explain how the list of control signals is supposed to interact, which signals are active high vs. active low, whether they are assumed to be synchronous or async etc.

I'm missing coverage of how exactly different subtle choices of writing the code affects the synthesis of the FPGAs in various ways, by way of examples that show what happens in those cases.

创建者 Adriel K

Mar 16, 2022

The course is OK, but the videos are terrible. The presenters do nothing more than just read the slides as they appear, which are sometimes just a page of code. In the VHDL section, I believe the presenter is seeing the material for the first time. I ended up just turning the audio off and treating the videos as a slide deck, which worked quite well. The assignments were fun.

创建者 Julien T

Dec 7, 2021

Interesting course but exercises shall be reworked as sometimes it's not clear what is the expected output so we end up guessing via the testbench. Another issue is that some half backed quizzes prevent you from practicing the exercises until you pass even though practicing is key to understand the concepts...

创建者 Islam E

May 31, 2020

this course need a person who knows before the basics of both VHDL/Verilog. because i know some basics of VHDL i understood its part but verilog was a little bit hard to me to understand it

创建者 Harsh A

Jun 15, 2020

Verilog part is explained very well but VHDL part completely unsatisfied.

创建者 Sachin A

Apr 21, 2020

Very introductory. Verilog and VHDL exercises are copied.

创建者 Sakshat R

May 28, 2020

Innovative teaching, but very poor assignments

创建者 Samuel C

Aug 14, 2020

A decent introduction to HDL.

创建者 Pushkar A

Sep 30, 2020

Teaching could be better.


Jul 11, 2021


创建者 Ryan B

Aug 5, 2022

The course material can be interesting. However, it's clear that they're looking to get as much paid subscription time from you. They lock off the actual programming assinments behind quizzes which, if you don't get enough right, they delay you for 3 days.

创建者 Nur Y Y

Sep 27, 2022

Assignments are not clear and I cannot open assignment files. Because of this I cannot finish the course. Also, ModelSim download link was not working. I have a lot of trouble about download.

创建者 Rishi D

Jun 12, 2020

teacher as well as way of teaching is not good . assignments are great though

创建者 Ethan R

Apr 11, 2020

The highlight of this course was the recommended reading materials.

创建者 Surabhi M

Nov 8, 2020

not clear.

创建者 saikumar s

Oct 31, 2020

There is no technical support

创建者 Muhammet M K

Aug 23, 2021